With the recent increased complexity of built-in devices, establishment of a technique for performing efficient debugging at the stage of development has been demanded. For debugging most built-in devices, a method of setting up a break point using an incircuit emulator (ICE), a method of executing steps, and others have been used. However, there are many cases in which these methods cannot be used because it is impossible to adapt the operation timing with the timing of the surrounding circuit when the system is required to have real-time properties.
Under such circumstances, an importance of the observation of the status change and the behavior by tracing the operation inside the device has being increased.
On the other hand, in order to reduce production cost of built-in devices, there are often the cases where they do not have much margin as to internal memory capacity and CPU performance. Therefore, the method of storing an operation log by software processing, which is used by usual computer equipment typified by servers and personal computers, cannot be satisfactorily used by a built-in device. Further, in built-in devices, a customized system LSI is often used, so that it is often important to make observation on the behavior of the bus, the behavior of the peripheral circuits and the like, which cannot be observed by software processing alone.
For this reason, usually a technique for extracting signals for checking the operational status of a system LSI through monitoring terminals is provided, and it is an effective method is to store the change of the operational status as traced data by using the monitoring terminals and to analyze it. A technology using this technique is disclosed in Japanese Patent Application Laid-open 2002-24201 (which will be referred to hereinbelow as “Document 1”).
FIG. 1 is a block diagram showing an internal configuration of a system LSI described in Document 1. The system LSI in FIG. 1 includes MPU core (control circuit) 91, built-in RAM (Random Access Memory, storage circuit) 92 that stores the program for operating MPU core 91, peripheral circuit 93 for performing transmission and reception of signals with MPU core 91. The system LSI is also connected to system LSI peripheral apparatus 5, so that the two transmit and receive signals to and from each other. Built-in RAM 92 also incorporates a debug supporting function program in addition to other than the program for operating MPU core 91.
Further, debug supporting circuit 914 incorporating signal selection circuit 931 is provided inside MPU core 91. Peripheral circuit 93 incorporates signal selection circuit 932. In addition, signal selection circuit 933 for selecting a final monitor signal is provided. The selecting operation of each of signal selection circuits 931 to 933 is controlled by monitor signal control circuit 4.
The system LSI in Document 1 includes signal selection circuit 931 for selecting any one of the internal signals in MPU core 91, signal selection circuit 932 for selecting any one of the internal signals in peripheral circuit 93 and signal selection circuit 933 for selecting either one of the outputs from these signal selection circuits 931 and 932, and the system LSI can arbitrarily switch the selecting operation of each of signal selection circuits 931 to 933 as required. Accordingly, it is possible to analyze in detail the internal operation of the system LSI in real-time. Further, even if the monitoring terminals are limited, it is possible to easily switch and output a plurality of monitoring signals.